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1.25 msps, 16 mw internal ref and clk, 12-bit parallel adc ad7492 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features specified for v dd of 2.7 v to 5.25 v throughput rate of 1 msps (ad7492) throughput rate of 1.25 msps (ad7492-5) throughput rate of 400 ksps (ad7492-4) low power 4 mw typ at 1 msps with 3 v supplies 11 mw typ at 1 msps with 5 v supplies wide input bandwidth 70 db typ snr at 100 khz input frequency 2.5 v internal reference on-chip clk oscillator flexible power/throughput rate management no pipeline delays high speed parallel interface sleep mode: 50 n a typ 24-lead soic and tssop packages functional block diagram v in db0 db11 ps/fs convst busy cs rd ad7492 a v dd ref out v drive agnd dgnd dv dd buf t/h output drivers 12-bit sar adc 2.5v ref clock oscillator control logic 01128-001 4 20 5 21 6 10 71 9 11 8 9 12 figure 1. general description the ad7492, ad7492-4, and ad7492-5 are 12-bit high speed, low power, successive approximation adcs. the parts operate from a single 2.7 v to 5.25 v power supply and feature throughput rates up to 1.25 msps. they contain a low noise, wide bandwidth track/hold amplifier that can handle bandwidths up to 10 mhz. the conversion process and data acquisition are controlled using standard control inputs allowing for easy interface to microprocessors or dsps. the input signal is sampled on the falling edge of convst and conversion is also initiated at this point. the busy pin goes high at the start of conversion and goes low 880 ns (ad7492/ad7492-4) or 680 ns (ad7492-5) later to indicate that the conversion is complete. there are no pipeline delays associated with the part. the conversion result is accessed via standard cs and rd signals over a high speed parallel interface. the ad7492 uses advanced design techniques to achieve very low power dissipation at high throughput rates. with 5 v supplies and 1.25 msps, the average current consumption ad7492-5 is typically 2.75 ma. the part also offers flexible power/throughput rate management. it is also possible to operate the part in a full sleep mode and a partial sleep mode, where the part wakes up to do a conversion and automatically enters a sleep mode at the end of conversion. the type of sleep mode is hardware selected by the ps/ fs pin. using these sleep modes allows very low power dissipation numbers at lower throughput rates. the analog input range for the part is 0 v to refin. the 2.5 v reference is supplied internally and is available for external referencing. the conversion rate is determined by the internal clock. product highlights 1. high throughput with low power consumption. the ad7492-5 offers 1.25 msps throughput with 16 mw power consumption. 2. flexible power/throughput rate management. the conversion time is determined by an internal clock. the part also features two sleep modes, partial and full, to maximize power efficiency at lower throughput rates. 3. no pipeline delay. the part features a standard successive approximation adc with accurate control of the sampling instant via a convst input and once-off conversion control. 4. flexible digital interface. the v drive feature controls the voltage levels on the i/o digital pins. 5. fewer peripheral components. the ad7492 optimizes pcb space by using an internal reference and internal clk.
ad7492 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ....................................................................... 1 revision history ........................................................................... 2 specifications..................................................................................... 3 ad7492-5 ...................................................................................... 3 ad7492/ad7492-4 ...................................................................... 4 timing specifications .................................................................. 6 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical peformance characteristics ............................................. 10 terminology .................................................................................... 12 circuit description......................................................................... 13 converter operation.................................................................. 13 typical connection diagram ................................................... 13 adc transfer function............................................................. 13 ac acquisition time ................................................................. 14 dc acquisition time................................................................. 14 analog input ............................................................................... 14 parallel interface......................................................................... 14 operating modes........................................................................ 14 power-up..................................................................................... 16 grounding and layout .............................................................. 18 power supplies ............................................................................ 18 microprocessor interfacing....................................................... 18 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 5/06rev. 0 to rev. a added ad7492-4................................................................universal changes to table 4............................................................................ 8 updated outline dimensions ....................................................... 22 changes to ordering guide .......................................................... 22 1/01revision 0: initial version
ad7492 rev. a | page 3 of 24 specifications ad7492-5 v dd = 4.75 v to 5.25 v, t a = t min to t max , unless otherwise noted. table 1. parameter a version 1 b version 1 unit test conditions/comments dynamic performance f s = 1.25 msps signal-to-noise and distortion (sinad) 69 69 db typ f in = 500 khz sine wave 68 68 db min f in = 100 khz sine wave signal-to-noise ratio (snr) 70 70 db typ f in = 500 khz sine wave 68 68 db min f in = 100 khz sine wave total harmonic distortion (thd) ?83 ?83 db typ f in = 500 khz sine wave ?87 ?87 db typ f in = 100 khz sine wave ?75 ?75 db max f in = 100 khz sine wave peak harmonic or spurious-free dynamic noise (sfdr) ?83 ?83 db typ f in = 500 khz sine wave ?90 ?90 db typ f in = 100 khz sine wave ?76 ?76 db max f in = 100 khz sine wave intermodulation distortion (imd) second order terms ?82 ?82 db typ f in = 500 khz sine wave ?90 ?90 db typ f in = 100 khz sine wave third order terms ?71 ?71 db typ f in = 500 khz sine wave ?88 ?88 db typ f in = 100 khz sine wave aperture delay 5 5 ns typ aperture jitter 15 15 ps typ full power bandwidth 10 10 mhz typ dc accuracy f s = 1.25 msps resolution 12 12 bits integral nonlinearity 1.5 1.25 lsb max differential nonlinearity +1.5/C0.9 +1.5/?0.9 lsb max guaranteed no missed codes to 12 bits (a and b versions) offset error 9 9 lsb max gain error 2.5 2.5 lsb max analog input input voltage ranges 0 to 2.5 0 to 2.5 v dc leakage current 1 1 a max input capacitance 33 33 pf typ reference output ref out output voltage range 2.5 2.5 v 1.5% for specified performance logic inputs input high voltage, v inh 2 v drive 0.7 v drive 0.7 v min v dd = 5 v 5% input low voltage, v inl 2 v drive 0.3 v drive 0.3 v max v dd = 5 v 5% input current, i in 1 1 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 3 10 10 pf max logic outputs output high voltage, v oh v drive ? 0.2 v drive ? 0.2 v min i source = 200 a output low voltage, v ol 0.4 0.4 v max i sink = 200 a floating-state leakage current 10 10 a max floating-state output capacitance 10 10 pf max output coding straight (natural) binary straight (natural) binary
ad7492 rev. a | page 4 of 24 parameter a version 1 b version 1 unit test conditions/comments conversion rate conversion time 680 680 ns max track/hold acquisition time 120 120 ns min throughput rate 1.25 1.25 msps max conversion time + acquisition time power requirements v dd 4.75/5.25 4.75/5.25 v min/max i dd digital i/ps = 0 v or dv dd normal mode 3.3 3.3 ma max f s = 1.25 msps, typ 2.75 ma quiescent current 1.8 1.8 ma max partial sleep mode 250 250 a max static, typ 190 a full sleep mode 1 1 a max static, typ 200 na power dissipation 4 digital i/ps = 0 v or dv dd normal mode 16.5 16.5 mw max partial sleep mode 1.25 1.25 mw max full sleep mode 5 5 w max 1 temperature ranges as follows: a and b versions: ?40c to +85c. 2 v inh and v inl trigger levels are set by the v drive voltage. the logic interfac e circuitry is powered by v drive . 3 sample tested @ 25c to ensure compliance. 4 see the power vs. throughput section. ad7492/ad7492-4 v dd = 2.7 v to 5.25 v, t a = t min to t max , unless otherwise noted. 1 table 2. parameter a version 2 b version 2 unit test conditions/comments dynamic performance f s = 1 msps for ad7492 f s = 400 ksps for ad7492-4 signal-to-noise and distortion (sinad) 69 69 db typ f in = 500 khz sine wave 3 68 68 db min f in = 100 khz sine wave signal-to-noise ratio (snr) 70 70 db typ f in = 500 khz sine wave 3 68 68 db min f in = 100 khz sine wave total harmonic distortion (thd) ?85 ?85 db typ f in = 500 khz sine wave 3 ?87 ?87 db typ f in = 100 khz sine wave ?75 ?75 db max f in = 100 khz sine wave peak harmonic or spurious-free dynamic noise (sfdr) ?86 ?86 db typ f in = 500 khz sine wave 3 ?90 ?90 db typ f in = 100 khz sine wave ?76 ?76 db max f in = 100 khz sine wave intermodulation distortion (imd) second order terms ?77 ?77 db typ f in = 500 khz sine wave 3 ?90 ?90 db typ f in = 100 khz sine wave third order terms ?69 ?69 db typ f in = 500 khz sine wave 3 ?88 ?88 db typ f in = 100 khz sine wave aperture delay 5 5 ns typ aperture jitter 15 15 ps typ full power bandwidth 10 10 mhz typ
ad7492 rev. a | page 5 of 24 parameter a version 2 b version 2 unit test conditions/comments dc accuracy f s = 1 msps for ad7492 f s = 400 ksps for ad7492-4 resolution 12 12 bits integral nonlinearity 1.5 lsb max 0.6 lsb typ v dd = 5 v 1 lsb max v dd = 3 v differential nonlinearity +1.5/?0.9 +1.5/?0.9 lsb max guaranteed no missed codes to 12 bits (a and b versions) offset error 9 9 lsb max gain error 2.5 2.5 lsb max analog input input voltage ranges 0 to 2.5 0 to 2.5 v dc leakage current 1 1 a max input capacitance 33 33 pf typ reference output ref out output voltage range 2.5 2.5 v 1.5% for specified performance logic inputs input high voltage, v inh 4 v drive 0.7 v drive 0.7 v min v dd = 5 v 5% input low voltage, v inl 4 v drive 0.3 v drive 0.3 v max v dd = 5 v 5% input current, i in 1 1 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 3, 5 10 10 pf max logic outputs output high voltage, v oh v drive ? 0.2 v drive ? 0.2 v min i source = 200 a output low voltage, v ol 0.4 0.4 v max i sink = 200 a floating-state leakage current 10 10 a max floating-state output capacitance 10 10 pf max output coding straight (natural) binary straight (natural) binary conversion rate conversion time 880 880 ns max track/hold acquisition time 120 120 ns min throughput rate 1 400 1 msps max ksps max conversion time + acquisition time for ad7492 conversion time + acquisition time for ad7492-4 power requirements v dd 2.7/5.25 2.7/5.25 v min/max i dd digital i/ps = 0 v or dv dd . normal mode 3 3 ma max f s = 1 msps, typ 2.2 ma f s = 400 ksps, typ 2.2 ma (ad7492-4) quiescent current 1.8 1.8 ma max partial sleep mode 250 250 a max static, typ 190 a full sleep mode 1 1 a max static, typ 200 na power dissipation 4, 6 digital i/ps = 0 v or dv dd normal mode 15 15 mw max v dd = 5 v partial sleep mode 1.25 1.25 mw max v dd = 5 v full sleep mode 5 5 w max v dd = 5 v 1 only a version specification applies to the ad7492-4. 2 temperature ranges as follows: a and b versions: ?40c to +85c. 3 500 khz sine wave specifications do not apply for the ad7492-4. 4 v inh and v inl trigger levels are set by the v drive voltage. the logic interfac e circuitry is powered by v drive . 5 sample tested @ 25c to ensure compliance. 6 see the power vs. throughput section.
ad7492 rev. a | page 6 of 24 timing specifications v dd = 2.7 v to 5.25 v, t a = t min to t max , unless otherwise noted. 1 table 3. limit at t min , t max parameter ad7492/ad7492-4 ad7492-5 2 unit description t convert 880 680 ns max t wakeup 20 3 20 3 s max partial sleep wake-up time 500 500 s max full sleep wake-up time t 1 10 10 ns min convst pulse width t 2 10 10 ns max convst to busy delay, v dd = 5 v 40 n/a ns max convst to busy delay, v dd = 3 v t 3 0 0 ns max busy to cs setup time t 4 4 0 0 ns max cs to rd setup time t 5 20 20 ns min rd pulse width t 6 4 15 15 ns min data access time after falling edge of rd t 7 5 8 8 ns max bus relinquish time after rising edge of rd t 8 0 0 ns max cs to rd hold time t 9 120 120 ns min acquisition time t 10 100 100 ns min quiet time 1 sample tested @ 25c to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v (see figure 2). 2 the ad7492-5 is specified with v dd = 4.75 v to 5.25 v. 3 this is the time needed for the part to settle within 0.5 lsb of its stable value. conversion can be initiated earlier than 20 s, but there is no guarantee that the part samples within 0.5 lsb of the true analog input value. therefore, the user should not start conversion until after the specifie d time. 4 measured with the load circuit of figure 2 and defined as the time required for the output to cross 0.8 v or 2.0 v 5 t 7 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 2. the meas ured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 7 , quoted in the timing characteri stics is the true bus relinquish time of the part and is in dependent of the bus loading. 1.6v 200a i ol to output pin c l 50pf 200a i oh 0 1128-002 figure 2. load circuit for digita l output timing specifications
ad7492 rev. a | page 7 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter ratings av dd to agnd/dgnd ?0.3 v to +7 v dv dd to agnd/dgnd ?0.3 v to +7 v v drive to agnd/dgnd ?0.3 v to +7 v av dd to dv dd ?0.3 v to +0.3 v v drive to dv dd ?0.3 v to dv dd + 0.3 v agnd to dgnd ?0.3 v to +0.3 v analog input voltage to agnd ?0.3 v to av dd + 0.3 v digital input voltage to dgnd ?0.3 v to dv dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range commercial (a and b versions) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c soic, tssop package dissipation 450 mw ja thermal impedance 75c/w (soic) 115c/w (tssop) jc thermal impedance 25c/w (soic) 35c/w (tssop) lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ad7492 rev. a | page 8 of 24 pin configuration and fu nction descriptions 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad7492 top view (not to scale) db9 db10 (msb) db11 av dd busy ps/fs ref out convst rd agnd cs v in db8 db7 db6 v drive db0 (lsb) db1 dv dd db2 db3 db5 db4 dgnd 01128-003 figure 3. pin configuration table 5. pin function descriptions pin mnemonic function 1 to 3, 13 to 18, 22 to 24 db11 to db0 data bit 11 to data bit 0. parallel digital outputs that provide the conver sion result for the part. these are three-state outputs that are controlled by cs and rd . the output high voltage le vel for these outputs is determined by the v drive input. 4 av dd analog supply voltage, 2.7 v to 5.25 v. this is the on ly supply voltage for all analog circuitry on the ad7492. the av dd and dv dd voltages should ideally be at the same poten tial and must not be more than 0.3 v apart, even on a transient basis. this supply should be decoupled to agnd. 5 ref out reference out. the output voltage from this pin is 2.5 v 1%. 6 v in analog input. single-ended analog input channel. the in put range is 0 v to refin. the analog input presents a high dc input impedance. 7 agnd analog ground. ground reference poi nt for all analog circuitry on th e ad7492. all analog input signals should be referred to this agnd voltage. the agnd and dgnd voltages should ideally be at the same potential and must not be more than 0. 3 v apart, even on a transient basis. 8 cs chip select. active low logic input used in conjunction with rd to access the conversion result. the conversion result is placed on the data bus following the falling edge of both cs and rd . cs and rd are both connected to the same and gate on the input so the signals are interchangeable. cs can be hardwired permanently low. 9 rd read input. logic input used in conjunction with cs to access the conversion result. the conversion result is placed on the data bus following the falling edge of both cs and rd . cs and rd are both connected to the same and gate on the input so the signals are interchangeable. cs and rd can be hardwired permanently low, in which case the data bus is always active and the result of the new conversion is clocked out slightly before to the busy line going low. 10 convst conversion start input. logic input used to initiate conversion. the input track/hold amplifier goes from track mode to hold mode on the falling edge of convst and the conversion process is initiated at this point. the conversion input can be as narrow as 10 ns. if the convst input is kept low for the duration of conversion and is still low at the end of conversion, the part automa tically enters a sleep mode. the type of sleep mode is determined by the ps/ fs pin. if the part enters a sleep mode, the next rising edge of convst wakes up the part. wake-up time depends on the type of sleep mode. 11 ps/ fs partial sleep/full sleep mode. this pin determines the type of sleep mode the part enters if the convst pin is kept low for the duration of the conversion and is still low at the end of conversion. in partial sleep mode the internal reference circuit and oscillator circuit are not powered down and draws 250 a maximum. in full sleep mode all of the analog circuitry are powered do wn and the current drawn is negligible. this pin is hardwired either high (dv dd ) or low (gnd). 12 busy busy output. logic output indicating th e status of the conversion process. the busy signal goes high after the falling edge of convst and stays high for the duration of the conversion. once the conversion is complete and the conversion result is in the output register, the busy line returns low. the track/hold returns to track mode just prior to the falli ng edge of busy and the acquisition time for the part begins when busy goes low. if the convst input is still low when busy goes low, the part automatically enters its sleep mode on the falling edge of busy. 19 dgnd digital ground. this is the ground reference point for all digital circuitry on the ad7492. the dgnd and agnd voltages should ideally be at the same potential and mu st not be more than 0.3 v apart, even on a transient basis.
ad7492 rev. a | page 9 of 24 pin mnemonic function 20 dv dd digital supply voltage, 2.7 v to 5.25 v. this is the su pply voltage for all digital circuitry on the ad7492 apart from the output drivers and input circuitry. the dv dd and av dd voltages should ideally be at the same potential and must not be more than 0.3 v apart even on a transient basis. this supply should be decoupled to dgnd. 21 v drive supply voltage for the output drivers and digital input circ uitry, 2.7 v to 5.25 v. this voltage determines the output high voltage for the data outp ut pins and the trigger levels for the digital inputs. it allows the av dd and dv dd to operate at 5 v (and maximize the dynamic perf ormance of the adc) while the digital input and output pins can interface to 3 v logic.
ad7492 rev. a | page 10 of 24 typical peformance characteristics input frequency (khz) 60 0 snr+d (db) 61 62 63 64 65 66 67 68 69 70 71 3v 5v 500 1000 1500 2000 2500 01128-004 figure 4. typical snr + d vs. input tone 50 thd (db) 55 60 65 70 75 80 85 90 95 3v 5v input frequency (khz) 100 200 350 500 1000 2000 0 1128-005 figure 5. typical thd vs. input tone supply (volts) 69.0 snr (db) 69.2 69.4 69.6 69.8 70.0 70.2 70.4 70.60 ?40c +25c ?55c +125c +85c 2.50 3.0 3.5 4.0 4.5 5.0 5.5 0 1128-006 figure 6. typical snr vs. supply ?120 (db) ?100 ?80 ?60 ?40 ?20 0 frequency (hz) 0 100000 200000 300000 400000 500000 600000 01128-007 figure 7. typical snr @ 500 khz input tone frequency (hz) ?3.5 (db) ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 5v 1 10 100 1000 10000 100000 0 1128-008 figure 8. typical bandwidth pssr (db) ?120 ?100 ?80 ?60 ?40 ?20 0 v cc = 5v 100mv p-p sinewave on v cc f sample = 1mhz, f in = 100khz v cc ripple frequency (khz) 0 5 10 16 20 26 31 36 41 46 51 57 61 67 72 77 82 88 92 97 3 8 13 18 23 28 34 39 44 49 54 59 64 69 74 80 84 89 94 100 01128-009 figure 9. typical power supply rejection ratio (psrr)
ad7492 rev. a | page 11 of 24 code 1.0 0 ?1.0 0 4089 ?0.8 3578 3067 2556 2045 1534 1023 512 ?0.6 ?0.4 ?0.2 0.2 0.4 0.6 0.8 01128-010 (inl) figure 10. typical inl for 2.75 v @ 25c code 1.0 0 ?1.0 0 4089 ?0.8 3578 3067 2556 2045 1534 1023 512 ?0.6 ?0.4 ?0.2 0.2 0.4 0.6 0.8 01128-011 (dnl) figure 11. typical dnl for 2.75 v @ 25c
ad7492 rev. a | page 12 of 24 terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, agnd + 1 lsb. gain error the last transition should occur at the analog value 1 1/2 lsb below the nominal full scale. the first transition is a 1/2 lsb above the low end of the scale (zero in the case of ad7492). the gain error is the deviation of the actual difference between the first and last code transitions from the ideal difference between the first and last code transitions with offset errors removed. track/hold acquisition time the track/hold amplifier returns into track mode after the end of the conversion. track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 0.5 lsb, after the end of conversion. signal-to-noise and distortion ratio this is the measured ratio of signal-to-noise and distortion at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal-to-noise and distortion = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db and for a 10-bit converter is 62 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7492 it is defined as: ( ) 1 2 6 2 5 2 4 2 3 2 2 log20)( v vvvvv dbthd ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n is equal to zero. for example, the second order terms include (fa + fb) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7492 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. aperture delay in a sample/hold, the time required after the hold command for the switch to open fully is the aperture delay. the sample is, in effect, delayed by this interval, and the hold command would have to be advanced by this amount for precise timing. aperture jitter aperture jitter is the range of variation in the aperture delay. in other words, it is the uncertainty about when the sample is taken. jitter is the result of noise that modulates the phase of the hold command. this specification establishes the ultimate timing error, hence the maximum sampling frequency for a given resolution. this error increases as the input dv/dt increases.
ad7492 rev. a | page 13 of 24 circuit description converter operation the ad7492 is a 12-bit successive approximation analog-to- digital converter based around a capacitive dac. the ad7492 can convert analog input signals in the range 0 v to v ref . figure 12 shows a very simplified schematic of the adc. the control logic, sar register, and capacitive dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. switches sar control logic comparato r v ref v in c ontrol inputs capacitive dac output data 12-bit parallel 01128-012 figure 12. simplified block diagram of ad7492 figure 13 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a. the comparator is held in a balanced condition and the sampling capacitor acquires the signal on v in . comparator control logic agnd 2k? sw2 sw1 a b v in capacitive dac 01128-013 figure 13. adc acquisition phase figure 14 shows the adc during conversion. when conversion starts, sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced. the adc then runs through its successive approximation routine and brings the comparator back into a balanced condition. when the comparator is rebalanced, the conversion result is available in the sar register. comparator control logic agnd sw2 sw1 a b 2k ? v in capacitive dac 01128-014 figure 14. adc conversion phase typical connection diagram figure 15 shows a typical connection diagram for the ad7492. conversion is initiated by a falling edge on convst . once convst goes low the busy signal goes high, and at the end of the conversion, the falling edge of busy is used to activate an interrupt service routine. the cs and rd lines are then activated in parallel to read the 12 data bits. the internal band gap reference voltage is 2.5 v, providing an analog input range of 0 v to 2.5 v, making the ad7492 a unipolar a/d. a capacitor with a minimum capacitance of 100 nf is needed at the output of the ref out pin as it stabilizes the internal reference value. it is recommended to perform a dummy conversion after power-up as the first conversion result could be incorrect. this also ensures that the part is in the correct mode of operation. the convst pin should not be floating when power is applied, as a rising edge on convst might not wake up the part. in figure 15 the v drive pin is tied to dv dd , which results in logic output voltage values being either 0 v or dv dd . the voltage applied to v drive controls the voltage value of the output logic signals and the input logic signals. for example, if dv dd is supplied by a 5 v supply and v drive by a 3 v supply, the logic output voltage levels would be either 0 v or 3 v. this feature allows the ad7492 to interface to 3 v parts while still enabling the a/d to process signals at 5 v supply. 100nf 2.5v 0v to 2.5v 1nf ad7492 ref out cs busy convst rd ++ c/p paralleled interface 10f 0.1f 47f av dd v drive dv dd v in a nalog supply 2.7v to 5.25v ps/fs 0 1128-015 db0 to db9 (db11) figure 15. typical connection diagram adc transfer function the output coding of the ad7492 is straight binary. the designed code transitions occur at successive integer lsb values (that is, 1 lsb, 2 lsb, etc.). the lsb size equals 2.5/4096 for the ad7492. the ideal transfer characteristic for the ad7492 is shown in figure 16 .
ad7492 rev. a | page 14 of 24 111...111 111...110 111...000 011...111 000...010 000...001 000...000 adc code analog input 1lsb = v ref /4096 0v 1/2lsb +v ref ?1lsb 01128-016 figure 16. transfer characteristic for 12 bits ac acquisition time in ac applications, it is recommended to always buffer analog input signals. the source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of the adc. large values of impedance at the v in pin of the adc cause the thd to degrade at high input frequencies. table 6. dynamic performance specifications input buffers snr 500 khz thd 500 khz typical amplifier current consumption ad9631 69.5 80 17 ma ad797 69.6 81.6 8.2 ma dc acquisition time the adc starts a new acquisition phase at the end of a conversion and ends it on the falling edge of the convst signal. at the end of the conversion, there is a settling time associated with the sampling circuit. this settling time lasts 120 ns. the analog signal on v in is also acquired during this settling time; therefore, the minimum acquisition time needed is 120 ns. figure 17 shows the equivalent charging circuit for the sampling capacitor when the adc is in its acquisition phase. r3 represents the source impedance of a buffer amplifier or resistive network, r1 is an internal switch resistance, r2 is for bandwidth control, and c1 is the sampling capacitor. c2 is back-plate capacitance and switch parasitic capacitance. during the acquisition phase the sampling capacitor must be charged to within 0.5 lsb of its final value. r3 v in r1 125? c1 22pf c2 8pf r2 636? 0 1128-017 figure 17. equivalent analog input circuit analog input figure 18 shows the equivalent circuit of the analog input structure of the ad7492. the two diodes, d1 and d2, provide esd protection for the analog inputs. the capacitor c3 is typically about 4 pf and can be primarily attributed to pin capacitance. the resistor r1 is an internal switch resistance. this resistor is typically about 125 . the capacitor c1 is the sampling capacitor while r2 is used for bandwidth control. d1 d2 v dd r1 125 ? c1 22pf c2 8pf r2 636 ? v in c3 4pf 01128-018 figure 18. equivalent analog input circuit parallel interface the parallel interface of the ad7492 is 12 bits wide. the output data buffers are activated when both cs and rd are logic low. at this point the contents of the data register are placed onto the data bus. figure 19 shows the timing diagram for the parallel port. figure 20 shows the timing diagram for the parallel port when cs and rd are tied permanently low. in this setup, once the busy line goes from high to low, the conversion process is completed. the data is available on the output bus slightly before the falling edge of busy. note that the data bus cannot change state while the a/d is doing a conversion, as this would have a detrimental effect on the conversion in progress. the data out lines go three-state again when either the rd or cs line goes high. thus the cs can be tied low permanently, leaving the rd line to control conversion result access. please reference the v drive section for output voltage levels. operating modes the ad7492 has two possible modes of operation depending on the state of the convst pulse at the end of a conversion, mode 1 and mode 2. mode 1 (high-speed sampling) in this mode of operation the convst pulse is brought high before the end of conversion, that is, before busy goes low (see figure 20 ). if the convst pin is brought from high-to-low while busy is high, the conversion is restarted. when operating in this mode a new conversion should not be initiated until 140 ns after busy goes low. this acquisition time allows the track/hold circuit to accurately acquire the input signal. as mentioned earlier, a read should not be done during a conversion. this mode facilitates the fastest throughput times for the ad7492.
ad7492 rev. a | page 15 of 24 busy cs rd dbx convst t 10 t 9 t 3 t 4 t 5 t 8 t 6 t 7 t convert t 2 01128-019 figure 19. parallel port timing convst busy dbx t convert t 2 t 9 data n data n+1 01128-020 figure 20. parallel port timing with cs and rd tied low mode 2 (partial or full sleep mode) figure 21 shows the ad7492 in mode 2 operation where the adc goes into either partial or full sleep mode after conversion. the convst line is brought low to initiate a conversion and remains low until after the end of the conversion. if convst goes high and low again while busy is high, the conversion is restarted. once the busy line goes from high-to-low, the convst line has its status checked and, if low, the part enters a sleep mode. the type of sleep mode the ad7492 enters depends on what way the ps/ fs pin is hardwired. if the ps/ fs pin is tied high, the ad7492 enters partial sleep mode. if the ps/ fs pin is tied low, the ad7492 enters full sleep mode. the device wakes up again on the rising edge of the convst signal. from partial sleep the ad7492 is capable of starting conversions typically 1 s after the rising edge of convst . the convst line can go from high-to-low during the wake-up time, but the conversion is still not initiated until after 1 s. it is recommended that the conversion should not be initiated until at least 20 s of the wake-up time has elapsed. this ensures that the ad7492 has stabilized to within 0.5 lsb of the analog input value. after 1 s, the ad7492 has only stabilized to within approxi- mately 3 lsb of the input value. from full sleep, this wake-up time is typically 500 s. in all cases the busy line only goes high once convst goes low. superior power performance can be achieved in these modes of operation by waking up the ad7492 only to carry out a conversion. the optimum power performance is obtained when using full sleep mode as the adc comparator, reference buffer, and reference circuit are powered down. while in partial sleep mode, only the adc comparator is powered down and the reference buffer is put into a low power mode. the 100 nf capacitor on the ref out pin is kept charged up by the reference buffer in partial sleep mode while in full sleep mode this capacitor slowly discharges. this explains why the wake-up time is shorter in partial sleep mode. in both sleep modes the clock oscillator circuit is powered down.
ad7492 rev. a | page 16 of 24 convst busy cs rd dbx t wakeup t convert 01128-021 figure 21. mode 2 operation v drive the v drive pin is used as the voltage supply to the digital output drivers and the digital input circuitry. it is a separate supply from av dd and dv dd . the purpose of using a separate supply for the digital input/output interface is that the user can vary the output high voltage, v oh , and the logic input levels, v inh and v inl , from the v dd supply to the ad7492. for example, if av dd and dv dd are using a 5 v supply, the v drive pin can be powered from a 3 v supply. the adc has better dynamic performance at 5 v than at 3 v, so operating the part at 5 v, while still being able to interface to 3 v parts, pushes the ad7492 to the top bracket of high performance 12-bit adcs. of course, the adc can have its v drive and dv dd pins connected together and be powered from a 3 v or 5 v supply. the trigger levels are v drive 0.7 and v drive 0.3 for the digital inputs. the pins that are powered from v drive are db11 to db0, cs , rd , convst , and busy. ps/ fs pin as previously mentioned, the ps/ fs pin is used to control the type of power-down mode that the ad7492 can enter into if operated in mode 2. this pin can be hardwired either high or low, or even controlled by another device. it is important to note that toggling the ps/ fs pin while in power-down mode does not switch the part between partial sleep and full sleep modes. to switch from one sleep mode to another, the ad7492 has to be powered up and the polarity of the ps/ fs pin changed. it can then be powered down to the required sleep mode. power-up it is recommended that the user performs a dummy conversion after power-up, as the first conversion result could be incorrect. this also ensures that the part is in the correct mode of operation. the recommended power-up sequence is as follows: 1. gnd 2. v dd 3. v drive 4. digital inputs 5. v in power vs. throughput the two modes of operation for the ad7492 produces different power vs. throughput performances, mode 1 and mode 2; see the operating modes section of the data sheet for more detailed descriptions of these modes. mode 2 is the sleep mode (partial/full) of the part and it achieves the optimum power performance. mode 1 figure 22 shows the ad7492 conversion sequence in mode 1 using a throughput rate of 500 ksps. at 5 v supply, the current consumption for the part when converting is 3 ma and the quiescent current is 1.8 ma. the conversion time of 880 ns contributes 6.6 mw to the overall power dissipation in the following way: (880 ns/2 s) (5 3 ma) = 6.6 mw the contribution to the total power dissipated by the remaining 1.12 s of the cycle is 5.04 mw (1.12 s/2 s) (5 1.8 ma) = 5.04 mw thus the power dissipated during each cycle is 6.6 mw + 5.04 mw = 11.64 mw convst busy 880ns t quiescent t convert 1.12s 2s 01128-022 figure 22. mode 1 power dissipation
ad7492 rev. a | page 17 of 24 mode 2 (full sleep mode) figure 23 shows the ad7492 conversion sequence in mode 2, full sleep mode, using a throughput rate of approximately 100 ksps. at 5 v supply the current consumption for the part when converting is 3 ma, while the full sleep current is 1 a maximum. the power dissipated during this power-down is negligible and thus not worth considering in the total power figure. during the wake-up phase, the ad7492 draws typically 1.8 ma. overall power dissipated is (880 ns/10 ms) (5 3 ma) + (500 s/10 ms) (5 1.8 ma) = 451.32 w convst busy 880ns 9.5ms 10ms t quiescent t convert 500s t wakeup 01128-023 figure 23. full slee p power dissipation mode 2 (partial sleep mode) figure 24 shows the ad7492 conversion sequence in mode 2, partial sleep mode, using a throughput rate of 1 ksps. at 5 v supply, the current consumption for the part when converting is 3 ma, while the partial sleep current is 250 a maximum. during the wake-up phase, the ad7492 typically draws 1.8 ma. power dissipated during wake-up and conversion is (880 ns/1 ms) (5 3 ma) + (20 s/1 ms) (5 1.8 ma) = 193.2 mw power dissipated during power-down is (979 s/1 ms) (5 250 a) = 1.22 mw overall power dissipated is 193.2 w + 1.22 mw = 1.41 mw convst busy 880ns 1ms t quiescent t convert 20s t wakeup 979s 01128-024 figure 24. partial sleep power dissipation figure 25 , figure 26 , and figure 27 show a typical graphical representation of power vs. throughput for the ad7492 when in mode 1 @ 5 v and 3 v, mode 2 in full sleep mode @ 5 v and 3 v, and mode 2 in partial sleep mode @ 5 v and 3 v. 0 700 2 4 6 8 10 12 800 400300200100 0 3v 5v power (mv) throughput (khz) 500 600 900 1000 01128-025 figure 25. power vs. throughput (mode 1 @ 5 v and 3 v) 3v 5v 0.5 70 1.0 1.5 2.0 2.5 3.0 3.5 80 40302010 0 power (mv) throughput (khz) 50 60 90 100 0 01128-026 figure 26. power vs. throughput (mode 2 in full sleep mode @ 5 v and 3 v) 3v 5v 0.5 70 1.0 1.5 2.0 2.5 80 4030 2010 0 power (mv) throughput (khz) 50 60 90 100 0 01128-027 figure 27. power vs. throughput (mode 2 in partial sleep mode @ 5 v and 3 v)
ad7492 rev. a | page 18 of 24 grounding and layout the analog and digital power supplies are independent and separately pinned out to minimize coupling between analog and digital sections within the device. to complement the excellent noise performance of the ad7492, it is imperative that care be given to the pcb layout. figure 28 shows a recommended connection diagram for the ad7492. all of the ad7492 ground pins should be soldered directly to a ground plane to minimize series inductance. the av dd pin, dv dd pin, and v drive pin should be decoupled to both the analog and digital ground planes. the ref out pin should be decoupled to the analog ground plane with a minimum capacitor value of 100 nf. this capacitor helps to stabilize the internal reference circuit. the large value capacitors decouple low frequency noise to analog ground, the small value capacitors decouple high frequency noise to digital ground. all digital circuitry power pins should be decoupled to the digital ground plane. the use of ground planes can physically separate sensitive analog components from the noisy digital system. the two ground planes should be joined in only one place and should not overlap so as to minimize capacitive coupling between them. if the ad7492 is in a system where multiple devices require agnd-to-dgnd connections, the connection should still be made at one point only, a star ground point, established as close as possible to the ad7492. ad7492 + 1nf 1nf + 100nf agnd dgnd ref out + + 2.5v analog supply 5v 47f 0.1f 10f 10f av dd dv dd v drive 01128-028 figure 28. typical decoupling circuit noise can be minimized by applying the following simple rules to the pcb layout: ? analog signals should be kept away from digital signals. ? fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. ? avoid running digital lines under the device as this couples noise onto the die. ? the power supply lines to the ad7492 should use as large a trace as possible to provide a low impedance path and reduce the effects of glitches on the power supply line. ? avoid crossover of digital and analog signals and place traces that are on opposite sides of the board at right angles to each other. noise to the analog power line can be further reduced by use of multiple decoupling capacitors as shown in figure 28 . decoupling capacitors should be placed directly at the power inlet to the pcb and also as close as possible to the power pins of the ad7492. the same decoupling method should be used on other ics on the pcb, with the capacitor leads as short as possible to minimize lead inductance. power supplies separate power supplies for av dd and dv dd are desirable, but if necessary, dv dd can share its power connection to av dd . the digital supply (dv dd ) must not exceed the analog supply (av dd ) by more than 0.3 v in normal operation. microprocessor interfacing adsp-2185 to ad7492 interface figure 29 shows a typical interface between the ad7492 and the adsp-2185. the adsp-2185 processor can be used in one of two memory modes, full memory mode and host mode. the mode c pin determines in which mode the processor works. the interface in figure 29 is set up to have the processor working in full memory mode, allowing full external addressing capabilities. when the ad7492 has finished converting, the busy line requests an interrupt through the irq2 pin. the irq2 interrupt has to be set up in the interrupt control register as edge- sensitive. the data memory select (dms) pin latches in the address of the adc into the address decoder. the read operation is started. address bus data bus 100k ? 1 additional pins omitted for clarity. optional address decoder ad7492 busy db0 to db9 (db11) convst cs rd adsp-2185 1 dms irq2 rd mode c d0 to d23 a0 to a15 01128-029 figure 29. adsp-2185 to ad7492 interface
ad7492 rev. a | page 19 of 24 adsp-21065lto ad7492 interface figure 30 shows a typical interface between the ad7492 and the adsp-21065l sharc? processor. this interface is an example of one of three dma handshake modes. the ms x control line is actually three memory select lines. internal addr25C24 are decoded into ms 3-0 , these lines are then asserted as chip selects. the dmar 1 (dma request 1) is used in this setup as the interrupt to signal end of conversion. the rest of the interface is standard handshaking operation. ad7492 address bus data bus 1 additional pins omitted for clarity. optional address decoder address latch address bus adsp-21065l 1 addr 0 to addr 23 ms x dmar 1 rd busy db0 to db9 (db11) convst cs rd d0 to 31 01128-030 figure 30. adsp-21065l to ad7492 interface tms320c25 to ad7492 interface figure 31 shows an interface between the ad7492 and the tms320c25. the convst signal can be applied from the tms320c25 or from an external source. the busy line interrupts the digital signal processor when conversion is completed. the tms320c25 does not have a separate rd output to drive the ad7492 rd input directly. this has to be generated from the processor strb and r/ w outputs with the addition of some glue logic. the rd signal is or-gated with the msc signal to provide the wait state required in the read cycle for correct interface timing. the following instruction is used to read the conversion from the ad7492: in d,adc where: d is the data memory address. adc is the ad7492 address. the read operation must not be attempted during conversion. address bus 1 additional pins omitted for clarity. optional data bus tms320c25 1 is strb ready msc r/w ad7492 address decoder busy db0 to db9 (db11) convst cs rd dmd0 to dmd15 a0 to a15 01128-031 figure 31. tms320c25 to ad7492 interface pic17c4x to ad7492 interface figure 32 shows a typical parallel interface between the ad7492 and pic17c4x. the microcontroller sees the adc as another memory device with its own specific memory address on the memory map. the convst signal can be controlled by either the microcontroller or an external source. the busy signal provides an interrupt request to the microcontroller when a conversion ends. the int pin on the pic17c4x must be configured to be active on the negative edge. port c and port d of the microcontroller are bidirectional and used to address the ad7492 and to read in the 12-bit data. the oe pin on the pic can be used to enable the output buffers on the ad7492 and perform a read operation. 1 additional pins omitted for clarity. optional pic17c4x 1 oe int ale ad7492 address latch busy db0 to db9 (db11) convst cs rd address decoder 01128-032 ad0 to ad15 figure 32. pic17c4x to ad7492 interface
ad7492 rev. a | page 20 of 24 80c186 to ad7492 interface figure 33 shows the ad7492 interfaced to the 80c186 microprocessor. the 80c186 dma controller provides two independent high speed dma channels where data transfer can occur between memory and i/o spaces. (the ad7492 occupies one of these i/o spaces.) each data transfer consumes two bus cycles, one cycle to fetch data and the other to store data. after the ad7492 has finished the conversion, the busy line generates a dma request to channel 1 (drq1). because of the interrupt, the processor performs a dma read operation that resets the interrupt latch. sufficient priority must be assigned to the dma channel to ensure that the dma request is serviced before the completion of the next conversion. this configuration can be used with 6 mhz and 8 mhz 80c186 processors. address/data bus data bus 1 additional pins omitted for clarity. r s q optional 80c186 1 rd drq1 ale ad0 to ad15 a16 to a19 ad7492 address decoder address latch address bus busy db0 to db9 (db11) convst cs rd 01128-033 figure 33. 80c186 to ad7492 interface
ad7492 rev. a | page 21 of 24 outline dimensions compliant to jedec standards ms-013-ad 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.020) 0.31 (0.012) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 24 13 12 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 15.60 (0.6142) 15.20 (0.5984) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. figure 34. 24-lead standard small outline package [soic_w] wide body (rw-24) dimensions shown in millimeters and (inches) 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 35. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model temperature range resolution (bits) throughput rate (msps) package description package option ad7492ar ?40c to +85c 12 1 24-lead soic_w rw-24 ad7492arCreel ?40c to +85c 12 1 24-lead soic_w rw-24 ad7492arCreel7 ?40c to +85c 12 1 24-lead soic_w rw-24 ad7492arz 1 ?40c to +85c 12 1 24-lead soic_w rw-24 ad7492arzCreel 1 ?40c to +85c 12 1 24-lead soic_w rw-24 ad7492arzCreel7 1 ?40c to +85c 12 1 24-lead soic_w rw-24 ad7492br ?40c to +85c 12 1 24-lead soic_w rw-24 ad7492br-reel ?40c to +85c 12 1 24-lead soic_w rw-24 ad7492brCreel7 ?40c to +85c 12 1 24-lead soic_w rw-24 ad7492brz 1 ?40c to +85c 12 1 24-lead soic_w rw-24 ad7492ar-5 ?40c to +85c 12 1.25 24-lead soic_w rw-24 ad7492ar-5Creel ?40c to +85c 12 1.25 24-lead soic_w rw-24
ad7492 rev. a | page 22 of 24 model temperature range resolution (bits) throughput rate (msps) package description package option ad7492ar-5Creel7 ?40c to +85c 12 1.25 24-lead soic_w rw-24 ad7492arz-5 1 ?40c to +85c 12 1.25 24-lead soic_w rw-24 ad7492br-5 ?40c to +85c 12 1.25 24-lead soic_w rw-24 ad7492br-5Creel ?40c to +85c 12 1.25 24-lead soic_w rw-24 ad7492br-5Creel7 ?40c to +85c 12 1.25 24-lead soic_w rw-24 ad7492brz-5 1 ?40c to +85c 12 1.25 24-lead soic_w rw-24 ad7492aru ?40c to +85c 12 1 24-lead tssop ru-24 ad7492aruCreel ?40c to +85c 12 1 24-lead tssop ru-24 ad7492aruCreel7 ?40c to +85c 12 1 24-lead tssop ru-24 ad7492aruz 1 ?40c to +85c 12 1 24-lead tssop ru-24 ad7492aruzCreel 1 ?40c to +85c 12 1 24-lead tssop ru-24 ad7492aruzCreel7 1 ?40c to +85c 12 1 24-lead tssop ru-24 ad7492aru-5 ?40c to +85c 12 1.25 24-lead tssop ru-24 ad7492aru-5Creel ?40c to +85c 12 1 .25 24-lead tssop ru-24 ad7492aru-5Creel7 ?40c to +85c 12 1.25 24-lead tssop ru-24 ad7492aruz-5 1 ?40c to +85c 12 1.25 24-lead tssop ru-24 ad7492aruz-5Creel 1 ?40c to +85c 12 1.25 24-lead tssop ru-24 ad7492aruz-5Creel7 1 ?40c to +85c 12 1.25 24-lead tssop ru-24 ad7492aruz-4 1 ?40c to +85c 12 0.4 24-lead tssop ru-24 ad7492aruz-4reel 1 ?40c to +85c 12 0.4 24-lead tssop ru-24 ad7492aruz-4reel7 1 ?40c to +85c 12 0.4 24-lead tssop ru-24 ad7492bru ?40c to +85c 12 1 24-lead tssop ru-24 ad7492bruCreel ?40c to +85c 12 1 24-lead tssop ru-24 ad7492bruCreel7 ?40c to +85c 12 1 24-lead tssop ru-24 ad7492bruz 1 ?40c to +85c 12 1 24-lead tssop ru-24 ad7492bru-5 ?40c to +85c 12 1.25 24-lead tssop ru-24 ad7492bru-5Creel ?40c to +85c 12 1.25 24-lead tssop ru-24 ad7492bru-5Creel7 ?40c to +85c 12 1.25 24-lead tssop ru-24 ad7492bruz-5 1 ?40c to +85c 12 1.25 24-lead tssop ru-24 eval-ad7492cb 2 evaluation board eval-control brd2 3 controller board 1 z = pbCfree part. 2 this can be used as a standalone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstration pu rposes. 3 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators.
ad7492 rev. a | page 23 of 24 notes
ad7492 rev. a | page 24 of 24 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d01128-0-5/06(a)

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